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| RF2461 0 Typical Applications * CDMA/FM (AMPS) Systems * Dual-Mode TACS/JCDMA Systems * General Purpose Downconverter Product Description The RF2461 is a receiver front-end designed for the receive section of dual-mode CDMA/FM cellular applications. It is designed to amplify and downconvert RF signals, while providing 30dB of stepped gain control range. Features include digital control of LNA gain, mixer gain, and power down mode. Another feature of the chip is adjustable IIP3 of the LNA and mixer using an off-chip current setting resistor. Noise figure, IP3, and gain are designed to be compatible with the IS-98B interim standard for CDMA cellular communications. The IC is manufactured on an advanced Silicon Germanium Bi-CMOS process and is assembled in a 4mmx4mm, 20-pin, QFN package. RoHS Compliant & Pb-Free Product CDMA/FM LOW NOISE AMPLIFIER/MIXER 900MHz DOWNCONVERTER * Commercial and Consumer Systems * Portable Battery-Powered Equipment 0.15 C A -A- 0.05 C 4.00 2 PLCS 1.00 0.90 2 PLCS 0.05 0.15 C B 3.75 4.00 Dimensions in mm. 12 MAX 0.15 C 2 PLCS -B- -C- 3.75 0.15 C 2 PLCS Note orientation of package. 0.10 M C A B 0.20 0.60 0.24 TYP 2 0.65 0.30 4 PLCS NOTES: 1 Shaded lead is Pin 1. Dimension applies to plated terminal: 2 to be measured between 0.02 mm and 0.25 mm from terminal end. 2.10 SQ. 0.75 0.50 0.50 0.23 0.13 4 PLCS Optimum Technology Matching(R) Applied Si BJT Si Bi-CMOS InGaP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS Package Style: QFN, 20-Pin, 4x4 Features * Complete Receiver Front-End * Stepped LNA/Mixer Gain Control ENABLE IP SET IF SEL VCC2 LO IN * Adjustable LNA/Mixer Bias Current * Adjustable LNA/Mixer IIP3 15 IF2+ 20 19 18 17 16 LNA GAIN 1 * Meets IMD Tests with Three Gain States/Two Logic Control Lines MIX GAIN 2 14 IF2- LNA IN 3 13 BYPASS VCC1 4 12 IF1+ Ordering Information RF2461 CDMA/FM Low Noise Amplifier/Mixer 900MHz Downconverter RF2461PCBA-41X Fully Assembled Evaluation Board RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com GND1B 5 11 IF1- 6 LNA OUT 7 ISET2 8 ISET1 9 GND3B 10 MIX IN Functional Block Diagram Rev B6 060925 8-103 RF2461 Absolute Maximum Ratings Parameter Supply Voltage Input LO and RF Levels Operating Ambient Temperature Storage Temperature Rating -0.5 to +5.0 +6 -40 to +85 -40 to +150 Unit VDC dBm C C Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s). Parameter Overall RF Frequency Range LO Frequency Range IF Frequency Range Power Down Current Specification Min. Typ. Max. 800 700 0.1 869 to 894 832 to 870 954 to 979 722 to 760 1000 1000 250 10 15.0 14.5 1.8 1.8 +11.0 +9.0 6.5 5.0 16.0 15.0 2 2 Unit MHz MHz MHz A dB dB dB dB dBm dBm mA mA LNA Gain=1 IPSET=1 IPSET=0 IPSET=1 IPSET=0 IPSET=1 IPSET=0 IPSET=1 IPSET=0 LNA Gain=0 Condition T = 25C, VCC =3.0V LNA - CDMA/JCDMA Gain Noise Figure Input IP3 Current +9.0 +7.0 14.0 13.5 LNA Bypass CDMA/JCDMA Gain Noise Figure Input IP3 Current -8 +16.0 -6 6 +18.0 0 8 dB dB dBm mA Mixer - CDMA Gain Noise Figure Input IP3 Current +3.0 +13.0 13 4 14.5 5.8 5.5 13 +4.0 +14.0 21 18 dB dB dB dB dBm dBm mA mA 7 14 Mixer - JCDMA Gain Noise Figure Input IP3 Current +2.0 +10.0 12 2.5 13 4.0 5.5 13 +3.0 +12.0 24 21 dB dB dB dB dBm dBm mA mA 7 14 3k balanced load. IIP3 is adjustable. Decreasing R4/R5 will increase IIP3. LO=965MHz@-10dBm, IF=85.38MHz Mixer Preamp ON, Mix Gain=1 Mixer Preamp OFF, Mix Gain=0 Mixer Preamp ON, Mix Gain=1 Mixer Preamp OFF, Mix Gain=0 Mixer Preamp ON, Mix Gain=1 Mixer Preamp OFF, Mix Gain=0 Mixer Preamp ON, Mix Gain=1 Mixer Preamp OFF, Mix Gain=0 3k balanced load. IIP3 is adjustable. Decreasing R4/R5 will increase IIP3. LOIN=741MHz@-4dBm, IF=110MHz Mixer Preamp ON, Mix Gain=1 Mixer Preamp OFF, Mix Gain=0 Mixer Preamp ON, Mix Gain=1 Mixer Preamp OFF, Mix Gain=0 Mixer Preamp ON, Mix Gain=1 Mixer Preamp OFF, Mix Gain=0 Mixer Preamp ON, Mix Gain=1 Mixer Preamp OFF, Mix Gain=0 8-104 Rev B6 060925 RF2461 Parameter Local Oscillator Input Input Level LO to IF Isolation LO to LNA Isolation -10 -70 -60 2.65 3.0 3.15 dBm dB dB V LNA High Gain/Mixer High Gain. LNA Gain=1, Mix Gain=1. Assumes 3dB Image filter insertion loss. 23.5 -11 26 2.4 -9 26 28 0 dB dB dBm mA LNA High Gain/Mixer Low Gain. LNA Gain=1, Mix Gain=0. Assumes 3dB Image filter insertion loss. 16.5 4.9 0 23 dB dB dBm mA LNA Low Gain/Mixer High Gain. LNA Gain=0, Mix Gain=1. Assumes 3dB Image filter insertion loss. 4 15.5 11.8 22 dB dB dBm mA LNA Low Gain/Mixer Low Gain. LNA Gain=0, Mix Gain=0. Assumes 3dB Image filter insertion loss. -7 +14 -4.5 22.5 +20 18 -3 40 dB dB dBm mA Specification Min. Typ. Max. Unit Condition Any gain state. Power Supply Voltage Cascade High Gain Mode Gain Noise Figure Input IP3 Current Cascade Mid Gain Mode Gain Noise Figure Input IP3 Current Cascade Low Gain Mode Gain Noise Figure Input IP3 Current Cascade Ultra-Low Gain Mode Gain Noise Figure Input IP3 Current Cellular CDMA, IPSET=1 Mode High Gain Mid Gain Low Gain Ultra-Low Gain LNA GAIN 1 1 0 0 MIX GAIN 1 0 1 0 Recommended for IMD Tests 1 and 2 Recommended for IMD Tests 3 and 4 Recommended for IMD Tests 5 and 6 Alternative Lowest Current Mode for IMD Tests 5 and 6 Rev B6 060925 8-105 RF2461 Pin 1 Function LNA GAIN Description Controls the bypass feature of the LNA. A logic low (<1.0V) selects the bypass mode. A logic high (>2.0V) turns on the LNA. Interface Schematic LNA GAIN 2 MIX GAIN Controls the bypass feature of the mixer preamp. A logic low (<1.0V) selects the bypass mode. A logic high (>2.0V) turns on the preamppreamp. LNA input pin. MIX GAIN 3 LNA IN LNA OUT LNA IN GND1B 4 5 VCC1 GND1B VCC pin for all circuits except the LO. Buffer/bias circuitry. LNA emitter. This pin provides the DC path to ground for the LNA. A lumped element or a transmission line inductor can be placed between this pin and ground to degenerate the LNA. This will decrease the gain and increase the IP3 of the LNA. As the value of inductance is increased, these effects will become more pronounced. LNA output pin. An external resistor R2 connected to this pin sets the current of the preamp and the mixer. An external resistor R3 connected to this pin sets the current of the LNA when IP SET is high (see pin 19). Ground pin for preamp circuit. A 3.3nH inductor is used between pin 9 and ground to degenerate the mixer preamp. Degenerating the preamp will reduce the gain, increase the IP3 and affect the preamp input impedance. MIX IN 6 7 8 9 LNA OUT ISET2 ISET1 GND3B See pin 3. VCC2 GND3B 10 11 12 MIX IN IF1IF1+ Mixer preamp input pin. Second differential output pin for the first mixer. First differential output pin for the first mixer. Open collector. A current combiner external network performs a differential to single-ended conversion and sets the output impedance. A DC blocking cap must be present if the IF filter input has a DC path to ground. Mixer (IF2+ and IF-) needs to "see" a differential impedance between 2k to 4k. See pin 9. See pin 12. IF1IF1+ 13 14 BYPASS IF2- Bypass pin for the LO bias reference. Second differential output pin for the second mixer. See pin 15. 8-106 Rev B6 060925 RF2461 Pin 15 Function IF2+ Description First differential output pin for the second mixer. Open collector. A current combiner external network performs a differential to single-ended conversion and sets the output impedance. A DC blocking cap must be present if the IF filter input has a DC path to ground. Mixer (IF2+ and IF2-) needs to "see" a differential impedance between 2k to 4k. Interface Schematic IF2IF2+ 16 17 VCC2 LO IN VCC pin for the LO buffer/bias circuitry. LO limiter input pin. LO IN 18 ENABLE This pin is used to enable or disable the RF2461. A logic high (>2.0V) enables the circuitry. A logic low (<1.0V) disables the circuitry. ENABLE 19 IP SET Controls the setting of the LNA current. A logic low (<1.0V) selects the internal resistance (49.5k), resulting in an LNA current of 5mA. A logic high (>2.0V) selects the external resistance at pin 8. Determines which IF port is active. A logic low (<1.0V) activates IF1 and deactivates IF2. A logic high (>2.0V) activates IF2 and deactivates IF1. Mixers are identical. Either IF output may be used for CDMA or AMPS applications. Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with multiple vias. IP SET 20 IF SEL IF SEL Pkg Base GND Rev B6 060925 8-107 RF2461 Application Schematic VCC2 NOTE: Microstrip Inductor, Z0 = 50 , L = 102 mils suggested compared values. See Note 7 100 pF 56 See Note 8 VCC1 L2 100 pF See Note 8 LO IN ENABLE IP SET IF SEL LNA GAIN 1 MIX GAIN See Note 11 IF2+ C2 L Filter IF2- 20 19 18 17 16 L1 15 R C1 4.3 nH LNA IN 16 nH See Note 12 2 33 nF 14 C1 3 13 BYPASS 100 pF 4 100 pF See Note 8 12 See Note 8 50 strip 5 L=130 mils W=12 mils Z0=50 See Note 2 VCC1 11 L1 6 7 8 9 10 R C1 C1 0.1 F 51 * *This resistor improves NF and IIP3 for VCC = 3.0 V. VCC1 See Note 8 See Note 9 100 pF 22 k 50 strip 620 See Note 10 See Note 4 47 k See Note 5 3.3 nH See Note 3 33 nF See Note 1 C2 L IF+ 7.5 nH L2 IFFilter VCC1 See Note 11 4 pF 47 nH See Note 6 100 pF See Note 8 Filter NOTES: 1. DC blocking capacitor. 2. LNA emitter degenerator. As the value of inductance is increased, the gain will decrease, and the IIP3 will increase. 3. Mixer preamp degeneration inductor. As the value of inductance is increased, the gain will decrease, and the IIP3 will increase. 4. An external resistor connected to this pin sets the current of the preamp and the mixer. Higher resistance to ground results in lower current. See chart at end of datasheet. 5. An external resistor connected to this pin sets the current of the LNA when IPSET is high. Higher resistance to ground results in lower current. See chart at end of datasheet. 6. Mixer input matching inductor. 7. LO input matching resistor. 8. Bypass capacitor. 9. LNA output matching and bias choke. 10. For stability of the LNA. 11. LNA input and output matching. 12. Low pass path to ground for two-tone beat frequency for optimum IIP3 of LNA. Output Interface Network L1, C1, and R form a current combiner which performs a differential to single-ended conversion at the IF frequency and sets the output impedance. In most cases, the resonance frequency is independent of R and can be set according to the following equation: fIF = 1 L1 2 (C1 + C ) EQ 2 where ROUT is the desired output impedance and RP is the parasitic equivalent parallel resistance of L1. C1 should be chosen as high as possible (not greater than 15pF), while maintaining an RP of L1 that allows for the desired ROUT. L2 and C2 serve dual purposes. L2 serves as an output bias choke, and C2 serves as a series DC block. In addition, L2 and C2 may be chosen to form an impedance matching network if the input impedance of the IF filter is not equal to ROUT. Otherwise, L2 is chosen to be large, and C2 is chosen to be large if a DC path to ground is present in the IF filter, or omitted if the filter is DC blocked. Where CEQ is the equivalent stray capacitance and capacitance looking into pins 11 and 12. An average value to use for CEQ is 2.5pF to 3pF. R can then be used to set the output impedance according to the following equation: R= (4 1 -1 R RP OUT )-1 Rev B6 060925 8-108 RF2461 Evaluation Board Schematic - CDMA LO@965MHz, RF@880MHz, IF@85MHz (Download Bill of Materials from www.rfmd.com.) P1 P1-1 1 2 P1-3 3 CON3 ENABLE IP SET IF SEL 20 LNA GAIN 1 MIX GAIN 329 pS Electrical Delay 0.10 dB Line Loss J2 LNA IN 50 strip 2 50 strip L1 4.3 nH L2 16 nH C1 33 nF 4 C2 100 pF VCC1 50 strip 5 L=130 mils W=12 mils Z0=50 11 50 strip L6 470 nH R4 10 k C9 11 pF 348 pS Electrical Delay @ 110 MHz 0.03 dB Line Loss J5 IF1 OUT 50 strip VCC1 C5 4 pF 50 strip 50 strip C6 33 nF 50 strip L5 47 nH C7 100 pF C10 11 pF 12 50 strip 3 13 50 strip BYPASS C11 100 pF 14 15 C12 11 pF 19 18 17 16 50 strip MIX GAIN GND LNA GAIN P2-1 P2-2 P2-3 P2 1 2 3 CON3 IF SEL IP SET ENABLE P3-3 P3-1 P3 1 2 3 CON3 50 strip 50 strip L9 470 nH R5 10 k 50 strip C14 10 pF VCC1 GND VCC2 447 pS Electrical Delay 0.13 dB Line Loss J1 LO IN R6 56 50 strip C16 100 pF L8 390 nH C15 100 pF 348 pS Electrical Delay @ 110 MHz 0.03 dB Line Loss J6 IF2 OUT 50 strip VCC2 VCC1 C13 11 pF 6 7 8 9 10 R14 51 VCC1 498 pS Electrical Delay 0.15 dB Line Loss J3 LNA OUT 50 strip Note: R14 improves NF and IIP3 for VCC = 3.0 V C3 0.1 F C4 100 pF L3 7.5 nH R1 620 50 strip 50 strip R2 18 k R3 47 k L4 3.3 nH 50 strip L7 390 nH C8 10 pF 320 pS Electrical Delay @ 880 MHz 0.10 dB Line Loss J4 MIXER IN Rev B6 060925 8-109 RF2461 Evaluation Board Schematic - JCDMA LO@741MHz, RF@851MHz, IF@110MHz P1 P1-1 1 2 P1-3 3 CON3 ENABLE IP SET IF SEL 20 LNA GAIN 1 MIX GAIN 329 pS Electrical Delay 0.10 dB Line Loss J2 LNA IN 50 strip 2 50 strip L1 4.3 nH L2 16 nH C1 33 nF 4 C2 100 pF VCC1 50 strip 5 L=130 mils W=12 mils Z0=50 11 50 strip L6 330 nH R4 4.3 k C9 9 pF 348 pS Electrical Delay @ 110 MHz 0.03 dB Line Loss J5 IF1 OUT 50 strip C10 11 pF 12 50 strip 3 13 50 strip BYPASS C11 100 pF 14 15 C12 10 pF 19 18 17 16 50 strip MIX GAIN GND LNA GAIN P2-1 P2-2 P2-3 P2 1 2 3 CON3 IF SEL IP SET ENABLE P3-3 P3-1 P3 1 2 3 CON3 50 strip 50 strip L9 330 nH R5 4.3 k 50 strip C14 7 pF VCC1 GND VCC2 447 pS Electrical Delay 0.13 dB Line Loss J1 LO IN R6 56 50 strip C16 100 pF L8 270 nH C15 100 pF 348 pS Electrical Delay @ 110 MHz 0.03 dB Line Loss J6 IF2 OUT 50 strip VCC2 VCC1 C13 9 pF 6 7 8 9 10 R14 51 VCC1 498 pS Electrical Delay 0.15 dB Line Loss J3 LNA OUT 50 strip Note: R14 improves NF and IIP3 for VCC = 3.0 V C3 0.1 F C4 100 pF L3 7.5 nH C5 4 pF R1 620 50 strip 50 strip R2 18 k R3 33 k L4 7.5 nH 50 strip L7 270 nH C7 100 pF 50 strip C6 33 nF 50 strip L5 30 nH C8 7 pF VCC1 50 strip 320 pS Electrical Delay @ 880 MHz 0.10 dB Line Loss J4 MIXER IN 8-110 Rev B6 060925 RF2461 Evaluation Board Layout Board Size 2.0" x 2.0" Board Thickness 0.031", Board Material FR-4, Multi-Layer Assembly Top Power Plane 1 Power Plane 2 Rev B6 060925 8-111 RF2461 Back 8-112 Rev B6 060925 RF2461 LNA Gain, Noise Figure and IIP3 versus ICC 16.0 Mixer Gain, Noise Figure and IIP3 versus ICC 15.0 25.00 20.00 10.0 15.00 5.0 5.00 LNA Only (LNA High Gain) Mixer (Mixer High Gain, LO=-7dBm) 10.00 14.0 Gain and Noise Figure (dB) Gain and Noise Figure (dB) 12.0 10.00 5.00 0.00 0.00 -5.00 -10.00 -5.00 Gain (dB) NF (dB) -15.00 IIP3 (dBm) -10.00 15.00 20.00 25.00 30.00 35.00 40.00 10.0 IIP3 (dBm) 0.0 8.0 -5.0 6.0 Gain (dB) NF (dB) 4.0 IIP3 (dBm) -15.0 -10.0 2.0 0.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 -20.0 16.0 -20.00 10.00 ICC (mA) ICC (mA) 200.0 180.0 160.0 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 0.0 2.0 Resistor (R3) versus ICC (mA) LNA Only (LNA High Gain) R3 (kohm) 200.0 180.0 160.0 140.0 Resistor (R2) versus ICC - Mixer (Mixer High Gain, LO=2170@-7dBm) R2 (kohm) Resistor R2 ( k) Resistor R3 (k) 120.0 100.0 80.0 60.0 40.0 20.0 0.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 ICC (mA) ICC (mA) Condition T=25oC, VCC=2.75V, RF=880 and 881MHz, LO=965MHz @-10dBm Rev B6 060925 8-113 IIP3 (dBm) RF2461 8-114 Rev B6 060925 |
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